Resumen de Towards the automatic synthesis of asynchronous communication mechanisms

Kyller Costa Gorgônio

• The correct transfer of data between concurrent processes is important in the exploitation of parallel architectures within distributed real-time systems. Techniques for solving this problem generally rely on mutual exclusion principles to control access to shared communication resources. The traditional solution involves the use of semaphores to protect write and read operations on a shared memory helping to preserve the data being transmitted.

  The problem with this approach is that a minimum locking between the asynchronous communicating processes is not guaranteed. This is mainly because the semaphore protects the data access operations. Since these operations may be performed in a register of arbitrary size, this may take a long time to conclude. One way of solving this problem is to design a communication scheme such that the atomic actions of each process occur at a very small granularity level, when accessing binary control variables.

  An AsynChronous Communication Mechanism (ACM) is a scheme which manages the transfer of data between two processes not necessarily synchronized. The general scheme includes a shared memory and a set of unidirectional control variables. Each control variable is set by one process and read by the other. This schema allows the design of communication protocols in which the processes are fully asynchronous. However, the use of binary control variables turns the implementation of ACMs a slow and prone to errors task.

  The construction of ACMs is known to be a hard task, and until now it was typically made on an ad-hoc basis using a construct-and-verify approach. This work introduces a technique for the automatic synthesis of ACMs, having as starting point only its functional specification. The result is an ACM implementation that can be used to communicate two asynchronous processes guaranteeing properties such as coherence and freshness. Coherence is related to the mutual exclusion between the communicating processes when accessing the communication buffer. Freshness is related to the fact that a written data must be made available for the reader.

  Two approaches for the automatic synthesis of ACMs are described. The first one is based on the generation of a state graph specification for the ACM. The state graph model captures the properties of an ACM at the level of interleaving semantics. Then a Petri Net (PN) model is synthesized from the state graph. The method for the synthesis of Petri nets is based on a more general procedure which uses the theory of regions. Finally, the implementation is derived from the PN.

  In this approach, the PN synthesized preserves coherence and freshness. This is guaranteed by construction. It is possible to generate state graph specifications of considerable size. However, the synthesis of PNs is only possible for ACMs of very small size. This makes the state graph based approach of limited practical use. From the analysis of the state graphs and the few PN models obtained, it was observed that both show a very regula structure. This regularity turned possible the directly generation of the PN models.

  Using this new approach, it is possible to generate bigger ACMs. The payback comes in the need to model check the PN before synthesizing the implementation. Coherence and freshness, are described as a set of CTl formulae, and model checking is applied over the PN. If the result is positive, the ACM synthesis can proceed. Since the state space of the ACMs grows very fast, this new approach suffers of the state space explosion problem. Then it happens, it is still possible to synthesize the ACM implementation, but it cannot be argued the correctness of coherence and freshness.

  The synthesis of ACM implementations is discussed for both software and hardware. Although the software is synthesized as C++ source code, the technique is generic enough to be used to obtain source code for any programming language. The hardware is synthesized in the form of Verilog code.