Logic synthesis techniques for high-speed circuits

• Autores: David Bañeres
• Directores de la Tesis: Jordi Cortadella Fortuny (dir. tes.) , Mike Kishinevsky (dir. tes.)
• Lectura: En la Universitat Politècnica de Catalunya (UPC) ( España ) en 2008
• Idioma: español
• Tribunal Calificador de la Tesis: Robert Nieuwenhuis (presid.) , Abelardo Pardo (secret.) , Iziano Villa (voc.) , Antonio Rubio (voc.) , Luciano Lavagno (voc.)
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• Resumen

  • Complexity in the design of electronic systems is significantly increasing in DSM technologies, Synthesis requires more powerful techniques to meet the specification constraints and capable to run in affordable time in the larger designs. One of the phases in VLSI design is logic synthesis. This thesis introduces several methods in this phase to meet one of the primary objectives in circuit design: timing optimization.

    Several contributions are presented. First, a solver of Boolean relations has been developed. A Boolean relation is able to capture more flexibility than conventional approaches based on don't cares. This work received the best paper award in the Design Automation Conference (DAC'04).

    The second contribution is a new partitioning algorithm based on the concept of vertex dominator. When optimization algorithms are applied on these clusters, this partition offers more possibilities for restructuring towards delay minimization compared to other techniques based on min-cut.

    A multi-level decomposition approach is also defined using the solver of Boolean relations: a timing-driven n-way decomposition. Functions are decomposed to improve the performance (speed) using a small library of multi-input gates.

    Finally, an integrated approach for layout-aware interconnect optimization is presented. This technique combines gate duplication and buffer insertion in the same framework with incremental placement. Similar to the principle of the Engineering Change Order (ECO), the circuit is incrementally improved by performing small modifications using fanout optimization techniques on top of the current placement.