Resumen de A visual simulation environment for MIPS based on VHDL
Jesús María Álvarez Llorente, Nieves Pavón Pulido, Julio Ballesteros Rubio
An application to perform a visual simulation of a machine based on MIPS is presented in this paper. The advantage of this system in relation to conventional simulators is that the simulation engine is the result of a real simulation under a VHDL development environment, so that hardware description can be modified and simulated in several ways to test and study its performance. So, it is possible to join the versatility of a commercial VHDL development tool with the simple handling of a graphic environment. In addition, an assembler language has been defined to write simple applications in order to test the simulated computer.
