Executing zero-delay branches with a Branch Target Buffer in a RISC processor

• Autores: Teodor Jové Lagunas, Jordi Cortadella Fortuny
• Localización: Mini and Microcomputers and their applications / Emilio Luque Fadón (ed. lit.) , 1988, págs. 373-376
• Idioma: inglés
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• Resumen

  • The execution of branch instructions is one of the main reasons that impede a steady flow of instructions in a pipelined processor. In this paper we propose a new mechanism based on a Branch Target Buffer for executing branches whit zero-time delay cost in RISC architectures. The performance of this mechanism is compared with that obtained by the delayed- branch tecnique. An analytical estimation and simulation results about the performance are presented. Over 20% of performance improvement is obtained in comparison whit those mechanisms based on the delayed-branch technique.