Presentation of AMARGO: an hierarchical VLSI physical layout synthesis system

• Autores: C. E. (Carlos Eduardo) Pereira, Dante Augusto Couto Barone
• Localización: Panel '92: actas, XVIII Conferencia Latinoamericana de Informática, 1992, págs. 961-968
• Idioma: inglés
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• Resumen

  • This work describes AMARGO, an hierarchical environment for general cell VLSI routing, which consists of a number of procedures as a global router, a router for power and ground lines and a channel router AMARGO belongs to the Cp2 project: Parallel Processing Contributions: Advances in Microelectronics and in Computer Architecture under development at the Instituto de Informática of the Federal University of Rio Grande do sul - Brazil