Evaluación de la fiabilidad de microprocesadores COTS mediante las infraestructuras de depuración On-Chip

• Isaza-González, José ^[1] ; Serrano-Cases, Alejandro ^[1] ; Restrepo-Calle, Felipe ^[2] ; Cuenca-Asensi, Sergio ^[1] ; Martínez-Álvarez, Antonio ^[1]
  1. [1] Universitat d'Alacant

     Universitat d'Alacant

     Alicante, España

     
  2. [2] Universidad Nacional de Colombia

     Universidad Nacional de Colombia

     Colombia

     
• Localización: Revista de I+D Tecnológico, ISSN-e 2219-6714, ISSN 1680-8894, Vol. 13, Nº. 1, 2017 (Ejemplar dedicado a: Revista I+D Tecnológico), págs. 5-14
• Idioma: español
• Títulos paralelos:
  • Dependability Evaluation of COTS Microprocessors via On-Chip debugging facilities
• Enlaces
  • Texto completo
• Resumen
  • español

    Este artículo presenta una herramienta de inyección de fallos y la metodología para la realización de campañas de inyección de Single-Event-Upsets (SEUs) en microprocesadores Commercial-off-the-shelf (COTS). Este método utiliza las ventajas que ofrecen las infraestructuras de depuración de los microprocesadores actuales, además del depurador estándar de GNU (GDB) para la ejecución y depuración de los programas de pruebas. Los experimentos desarrollados sobre microprocesadores reales, así como en las máquinas virtuales, demuestran la viabilidad y la flexibilidad de la propuesta como una solución de bajo costo para evaluar la fiabilidad de los microprocesadores COTS

  • English

    This paper presents a fault injection tool and methodology for performing Single-Event-Upsets (SEUs) injection campaigns on Commercial-off-the-shelf (COTS) microprocessors. This method takes advantage of the debug facilities of modern microprocessors along with standard GNU Debugger (GDB) for executing and debugging benchmarks. The developed experiments on real boards, as well as on virtual machines, demonstrate the feasibility and flexibility of the proposal as a low-cost solution for assessing the reliability of COTS microprocessors

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